Codebase
eXtensible Heterogeneous Energy-Efficient Platform based on RISC-V
https://github.com/x-heep/x-heep
137 forks.
272 stars.
129 open issues.
Recent commits:
- Remote upload of the bitstream from PYNQ utils (#862)* Added fusesoc flag 'ps' to build for Pynq-z2 with PS enabled for remote programming with PYNQ* Added fusesoc flag 'ps' to build for Pynq-z2 with PS enabled for remote programming with PYNQ* Added fusesoc flag 'ps' to build for Pynq-z2 with PS enabled for remote programming with PYNQ* Added doc + support for aup-zu3* Tested remote upload pynq-z2 & aup-zu3* verible run* Added JTAG, GPIO and UART to PS* Added JTAG, GPIO and UART to PS* Added JTAG, GPIO and UART to PS fo Pynq* Added JTAG, GPIO and UART to PS fo Pynq* Fixed ps_generation script* Fix pinout* Fix linter* Jtag connected and seems to work* Jtag connected and seems to work* Jtag connected* Added interrupt for uart* Added interrupt for uart* Added interrupt for uart* Added interrupt for uart fixed on right position* Xilinx interface for zynq works, to set-upo for ultrascale* Moved interrupt ID for ultrascale+* Clean up wrapper module* Added SPI for external flash programming from PS* Fix ECO* Fix ECO* Fix ECO* Fix ECO* Added eco to Pynq-z2 board* Clean-up* Fix ECO* Fix eco, broke verible* Removed comments from eco* Merge with main* Vendor update* merge main* Remove wrongly pushed files* Remove wrongly pushed files* Improved documentation on eco scripts* Fix wrongly updated files* Fix wrongly updated common xdc* Fix wrongly updated common xdc linter* Fix wrongly lintered wrapper* Fix wrongly lintered wrapper* Added deleted comment* Update readme warning* Update readme* Moved PS_ENABLE from FuseSOC FLAGS to ARGS* Update doc* Update PS-hook tcl---------Co-authored-by: Luigi Giuffrida <32927727+LuigiGiuffrida98@users.noreply.github.com>Co-authored-by: Luigi Giuffrida <luigi.giuffrida.98@gmail.com>, GitHub
- 🧱Move xheep_gen to different repository (#882)Co-authored-by: David Mallasén <david.mallasen@epfl.ch>, GitHub
- Allow pads to depend from X-HEEP config (#962), GitHub
- Add missing file for fpnew (#961), GitHub
- Separate register to AXI bridges in dedicated `.core` file (#960)* Separate register to AXI bridges core file* Improve core file name* Add back register interface deifinitions, GitHub
X-HEEP-based FPGA EMUlation Platform (FEMU).
https://github.com/esl-epfl/x-heep-femu
6 forks.
9 stars.
2 open issues.
Recent commits:
- Few changes., Simone Machetti
- Merge pull request #1 from JuanSapriza/pr_docsdAdded documentation about loading and using the SD card image., GitHub
- Merge pull request #7 from denizkasap/gpio_virtualizationGPIO Virtualization., GitHub
- clock domain crossing added for all signals, denizkasap
- error fix, denizkasap
X-HEEP-based FPGA EMUlation Platform (FEMU) Software Development Kit (SDK).
https://github.com/esl-epfl/x-heep-femu-sdk
11 forks.
3 stars.
1 open issues.
Recent commits:
- Merge pull request #9 from denizkasap/linker_ddrMemory Expansion of X-HEEP with DDR., GitHub
- Merge pull request #6 from esl-epfl/ext_ramPR review., GitHub
- Few changes., Simone Machetti
- Merge branch 'linker_ddr' of github.com:denizkasap/x-heep-femu-sdk into ext_ram., Simone Machetti
- Merge pull request #7 from denizkasap/gpio_virtualizationGPIO Virtualization., GitHub
Poster - October 2023
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