Codebase
eXtensible Heterogeneous Energy-Efficient Platform based on RISC-V
https://github.com/x-heep/x-heep
145 forks.
300 stars.
140 open issues.
Recent commits:
- Show file list in CI git diff (#1030), GitHub
- Add AGENTS.md and PR template (#1029), GitHub
- Fix length of ext_slaves address region in python (#1028), GitHub
- Add Support for Xilinx VPK180 Versal FPGA (#986)* Added fusesoc flag 'ps' to build for Pynq-z2 with PS enabled for remote programming with PYNQ* Added fusesoc flag 'ps' to build for Pynq-z2 with PS enabled for remote programming with PYNQ* Added fusesoc flag 'ps' to build for Pynq-z2 with PS enabled for remote programming with PYNQ* Added doc + support for aup-zu3* Tested remote upload pynq-z2 & aup-zu3* verible run* Added JTAG, GPIO and UART to PS* Added JTAG, GPIO and UART to PS* Added JTAG, GPIO and UART to PS fo Pynq* Added JTAG, GPIO and UART to PS fo Pynq* Fixed ps_generation script* Fix pinout* Fix linter* Jtag connected and seems to work* Jtag connected and seems to work* Jtag connected* Added interrupt for uart* Added interrupt for uart* Added interrupt for uart* Added interrupt for uart fixed on right position* Xilinx interface for zynq works, to set-upo for ultrascale* Moved interrupt ID for ultrascale+* Clean up wrapper module* Added SPI for external flash programming from PS* Fix ECO* Fix ECO* Fix ECO* Fix ECO* Added eco to Pynq-z2 board* Clean-up* Fix ECO* Fix eco, broke verible* Removed comments from eco* Merge with main* Vendor update* merge main* Remove wrongly pushed files* Remove wrongly pushed files* Improved documentation on eco scripts* Fix wrongly updated files* Fix wrongly updated common xdc* Fix wrongly updated common xdc linter* Fix wrongly lintered wrapper* Fix wrongly lintered wrapper* Added deleted comment* Update readme warning* core file updated with support of vpk180* xilinx wrapper and clock gating modifications* constraints and pin assignments added for versal FPGA* ps generation script is added* core files updated for vpk180* Update readme* two tcl files issue under invesitagtion* tcl handling updated, if PS_ENABLE=1, only genrate_ps_wizard.tcl will be executed* genenrate ps script is under inverstigation* UART connection to PS is corrected now* xilinx_generate_ps_wizard.tcl is now properly configured for Versal FPGAs, but FuseSoC support remains unclear.* implementation is done, QSPI pins are not connected and led to DRC error* a way of connecting external clock has been found to use clocking wizard. changing clock conenctions and clock wizard design* moving to the server for the synthesis* Moved PS_ENABLE from FuseSOC FLAGS to ARGS* Update doc* Update PS-hook tcl* commented some pin constraints* crash on local pc, still external buffers making problem and spi is hard to be removed directly* clock issue is almost resolved by removing I2C and I2s and SPI modules, avoiding the share usage of a pin for spi clock. yet reset has problem* Adding NOC* LPDDR is now using the differential clock and we have to find another source of clock for X-HEEP* wrapper updated for two lpddr clocks, reset corrected, constarints are updated, reset generation logic is simplified to avoid the usage of BUFGMUX for reset signals for the issues on Versal* constriants updated* reset led reveresed to show the latest changes.* xheep hello wolrd worked finally clear!* generate ps wizard updated* cleaned repository. xheep frequency is back to 50 MHz* sram wrapper is updated to support bram uram choice. moving to test embedded memory generator ip* NO_DDR_CLK_PORTS hadneld in core files for vpk180 target* rstgen_bypass reverted to the upstream and handled via new module vpk180_rstgen* tpl file of xheep system updated for conditional resetgen module instanciation* Pass the target to mcu-gen, to parse the appropriate SRAM-generator Tcl template based on the FPGA target.* using ps generated clock now for xheep* using pl clock led to an implementation phase deadlock, will be checked later. For now changes are reverted to work on SPI clocks first* sram wrapper tpl file was overriding memory changes* memory type parameter is removed again.* sram tcl generation flow reverted. vpk180 uses a special script for sram ip generation now* moving to server to test DDR ports* pulp obi package is included for proper usage of the bridge* replacing external bus with a single cross bar for now* address remapping is done in AXI NOC now instead of the obi to axi bridge* DDR test is done! XHEEP read the same values from the DDR written by PS* vendorization of axi_obi and obi are moved outside pulp directory* updating ddr to support more space* upgrading to use 8 GB RAM instead with 2 GB reserved for XHEEP* address mapping is corrected for 8GB access on CIPS* external slave range was configured wrong clear!* PULP obi package renaming is reverted. scripts and filed are adapted to the new directory structure in fpga/* default PS_ENABLE set fpr vpk180 target* obi types are set in top module wrapper of xilinx ow* license header comments are udpated. removed redundant directives in the core file* patch updated to support segmented configuration* disabling pl-related noc configs during boot* updated the tcl file. trying to resolve the pl ddr access issue solely* clock placement place and route error!* Requested changes applied, false paths need to be investigated yet* general.py reverted to the default version* updated changes based on reviews to the PR. Modification + Cleaning still in progress* Updated changes based on reviews* Doc is in progress. TCL hook added for clk_int_div buffering issue. Must be checked on multiple usage and/or no instance available during synthesis* Doc in progress. python config external address mapping alogigned to hjson files. Address Remapping of xheep corrected in tcl file* ddr test xw-xr, and psw-xr successful! Moving to make more extensive tests* ddr test added with specfic linker section. Doc updated* updated the docs* Minor improvements* Petalinux flow update* Docs updated with more info on vpk180* Update docs* constaints updated, petlainux openocd patch added to the scripts* petaliunux docs updated* Petalinux doc updated* Petalinux doc is updated* Enforce order of VPK180 instructions in the docs* Reorder FPGA docs* minimal updates to the Docs* Add UART filesystem overlay* Petalinux doc updated* petalinux doc is updated* Vendors are up to date. synced with PR on xheep-fpga-support* Vendors are updateed. FPGA scripts are now used from the new merged commit of xheep-fpga-support. Petalinux Docs are also updated to avoid confusion* Petalinux doc updated due to the encountered bugs during beta testing* Fix pin name in testbench* Push default configuration* removed extra pad config + doc improvement---------Co-authored-by: Christian Conti <christian.conti@polito.it>Co-authored-by: Christian Conti <116626662+Christian-Conti@users.noreply.github.com>Co-authored-by: Luigi Giuffrida <32927727+LuigiGiuffrida98@users.noreply.github.com>Co-authored-by: Luigi Giuffrida <luigi.giuffrida.98@gmail.com>Co-authored-by: nikkhahg <mohammadhossein.nikkhahghomi@epfl.ch>Co-authored-by: Michele Caon <michele.caon@epfl.ch>, GitHub
- Portability edit (#1026), GitHub
X-HEEP-based FPGA EMUlation Platform (FEMU).
https://github.com/esl-epfl/x-heep-femu
6 forks.
9 stars.
2 open issues.
Recent commits:
- Few changes., Simone Machetti
- Merge pull request #1 from JuanSapriza/pr_docsdAdded documentation about loading and using the SD card image., GitHub
- Merge pull request #7 from denizkasap/gpio_virtualizationGPIO Virtualization., GitHub
- clock domain crossing added for all signals, denizkasap
- error fix, denizkasap
X-HEEP-based FPGA EMUlation Platform (FEMU) Software Development Kit (SDK).
https://github.com/esl-epfl/x-heep-femu-sdk
11 forks.
3 stars.
1 open issues.
Recent commits:
- Merge pull request #9 from denizkasap/linker_ddrMemory Expansion of X-HEEP with DDR., GitHub
- Merge pull request #6 from esl-epfl/ext_ramPR review., GitHub
- Few changes., Simone Machetti
- Merge branch 'linker_ddr' of github.com:denizkasap/x-heep-femu-sdk into ext_ram., Simone Machetti
- Merge pull request #7 from denizkasap/gpio_virtualizationGPIO Virtualization., GitHub
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