In the realm of wearable healthcare devices, a sophisticated co-design approach that seamlessly integrates hardware and software components is essential to meet their stringent energy, area, and timing constraints. Prototyping tools play a pivotal role in this collaborative process, enabling engineers to iteratively test and optimize both the hardware and software functionalities of these devices. By using these tools, developers can systematically address challenges related to power consumption, spatial requirements, and timing precision, ensuring that the wearable devices not only meet but exceed the specified constraints. This iterative prototyping methodology not only expedites the development timeline but also facilitates the early identification and resolution of potential issues, contributing to the creation of highly efficient and reliable embedded systems for wearable healthcare applications.
On the aforementioned context, the Embedded System Laboratory (ESL) at Ecole Polytechnique Fédérale de Lausanne (EPFL) is developing different specifications of medical wearables using a common set of tools and a new open-source hardware frameworks to tackle the next-generation IoT devices by providing ultra-low-power and low-cost embedded solutions. In this project, the main idea is to provide prototyping tools to software and hardware developers using this new X-HEEP framework.
The tasks assigned for this project aim to enhance existing tools developed by ESL through processes such as automation, aligning hardware with software requirements, and vice versa.
Throughout their tenure at ESL, the student will:
- Gain insights into the diverse abstraction levels within an embedded system project like X-HEEP.
- Automate processes using Python and Bash scripts.
- Port X-HEEP to a potent FPGA, specifically the Ultrascale+.
- Design a framework for hardware emulation to be seamlessly integrated into the FEMU.
The project will be carried out at the ESL at EPFL, one of the world’s top-class universities. ESL is an active group (24 Ph.D. students among 45 members) involved in many research aspects. The student will be under the supervision of Mr. Simone Machetti as key daily supervisor, Mr. Juan Sapriza, Dr. José Miranda and Prof. David Atienza.
Project objectives:
- FEMU Update (3 months)
- Automate bitstream generation for the FEMU.
- Update the FEMU SDK to align with the latest X-HEEP SDK version.
- Update the hardware interface between the FEMU and the latest X-HEEP version.
- Re-compile the SD image to include the possibility of using sshfs.
- X-HEEP Porting (1.5 months)
- Port X-HEEP to a more powerful FPGA, specifically Ultrascale+.
- Update FEMU for compatibility with the new FPGA.
- Peripheral/Accelerator Emulation (1.5 months)
- Transform the CGRA simulator into a hardware emulation platform.
- Design a framework for seamless integration of additional hardware emulators.
- Integrate time, area, and energy estimations into the CGRA emulator.
Required knowledge and skills:
- Basic Python and Bash scripting.
- Basic Linux usage.
- Understanding of computer architecture and RTL.
Appreciated skills:
- Knowledge of SystemVerilog.
- Experience with FPGAs.
- Strong organizational and work habits.
- Advanced English.
Type of work: 80% technical development, 20% framework design.
Project duration: 6 months, at a 15 hs/week workload.
Supervisor: Mr. Simone Machetti, Mr. Juan Sapriza, Dr. Jose Miranda, Prof. David Atienza
Contact email: simone.machetti@epfl.ch,juan.sapriza@epfl.ch,jose.mirandacalero@epfl.ch,david.atienza@epfl.ch